Semiconductor devices face a number of challenges during the formation of a plurality of device package dies on a wafer. This is particularly the case for chip scale package metal oxide semiconductor field effect transistor (MOSFET) devices, especially vertical conduction power MOSFET devices having gate and source regions on one surface of a semiconductor substrate and a drain region on the opposite surface.
Electrical connections on one surface of a given semiconductor device and electrical connections on the other surface of the device must be extended to a common plane to allow for post-packaging use of the device. Extending back surface connections to the front surface of a given semiconductor device increases the device package size, and when performed on a wafer level, reduces the number of semiconductor device package dies that can fit on a given wafer. For semiconductor devices such as vertical conduction power MOSFET devices, it is desirable to work towards a smaller land pattern/minimized footprint and a smaller package thickness. This allows for a single wafer to fit a greater number of semiconductor device package dies, thus moving towards an optimal true chip scale package. It is similarly desirable to have a smaller electrical resistance associated with each semiconductor device package die. This may be accomplished by avoiding traditional wire bonding interconnections and by reducing the thickness of the semiconductor device package die. Better thermal dissipation is another desirable feature for semiconductor device package dies, and this can be achieved by using bottom and top exposure. Another desired result is providing greater support to the semiconductor device. Greater stability associated with greater support will also minimize the risk of chipping the semiconductor device chip/substrate. Lastly, it is important that the fabrication of these semiconductor device package dies be accomplished as a wafer level batch process in order to maximize efficiency and minimize the time needed to produce these semiconductor device package dies.
For semiconductor devices with multiple connections on one surface and one connection on the opposite surface (e.g., MOSFET device), achieving the desired features discussed above will require novel arrangement in extending connections to a common plane. It is also generally desirable to have simple, quick, and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old packaging technology continues as the primary packaging means. Epoxy or solder die attachment along with aluminum or gold wire bonding to a lead frame is still the dominant semiconductor packaging methodology. Advances in semiconductor processing technology, however, have made parasitics (e.g., resistances, capacitances, and inductances) associated with conventional packaging techniques more of a performance-limiting factor. In the case of conventional flip chip technology, among other shortcomings, electrical connection to the back side of the device is not easily facilitated while keeping a small footprint. These limitations become quite significant in high current applications such as power switching devices.
US publication number 2003/052405 discloses a vertical power MOSFET device with the drain electrode formed on the bottom surface of the silicon substrate connected to the lead frame above it, whereas the source electrode and the drain electrode are exposed to the bottom of the device. The MOSFET device is sealed by a resin, such as epoxy or silicone, such that the MOSFET device and an inner part of the lead frame are covered. On the bottom surface of the MOSFET device, the surface of the resin is approximately flush with surfaces of the lead frame and gate/source electrodes. That is, on the bottom surface of the semiconductor device, the bottom surface of outer lead portions of the lead frame and bottom surfaces of gate/source electrodes are exposed for connection to a conducting pad (mount surface) of the mounting substrate. Then the perimeter of these gate/source electrodes is covered by the resin.
U.S. Pat. No. 6,133,634 discloses a flip chip package having a power MOSFET device including a drain terminal, a source terminal, and a gate terminal. The drain terminal connects to a conductive carrier and an outer array of solder balls. The source terminal and gate terminal connect to an inner array of solder balls. The conductive carrier and the outer array of solder balls provide electrical connection to the drain terminal in the same plane as electrical connections to the source terminal and gate terminal.
The preceding prior art package designs for vertical power MOSFET devices can provide electrical interconnection for source, gate and drain for individual MOSFETs. However, additional assembly steps are needed after a wafer has been singulated into individual dies, which precludes further wafer level processing, which increases costs and fabrication time. In addition, the use of metal clips to provide drain contacts from the back to front sides of the die can reduce the available space for the device in a device package die. It would be desirable to produce a package design and process for its manufacture which permits wafer level processing with lower costs and a reduced footprint for individual part.
It is within this context that embodiments of the present invention arise.